Projects

Roman Number Calculator

Develop Program for addition and subtraction of Roman Numbers. You should follow Test driven development approach.

Environment:

OS : Ubuntu

Programming Language: C Compiler: GCC Unit testing Framework: Check (https://libcheck.github.io/check/)

Roman Number System Rules:

  1. It can only consist of I,V,X,L,C,D,M which converts to 1,5,10,50,100,500,1000 respectively.
  2. There are nothing like decimal or integers in Roman number strings so inputs will be strings.
  3. In Roman number system if lesser numeral is placed before higher value number then its conversion to decimal would be >> Big Number – small number <<
  4. For numeral I, X or C there should not be more then three consecutive I, X, or C i.e if “II” + “II” = “IV” not “IIII” but “II” + ‘I’ = “III”.

Reachability Analysis of Sequential Circuit using Monolithic Transition Relation and its Image Computation

Reachability Analysis is basic and fundamental technique for equivalence checking of sequential circuit. This paper presents the use of symbolic reachability analysis or symbolic state space traversal where binary decision diagrams are used to represents transition relation. This paper presents use of monolithic TR and early quantification TR for reachability analysis. It uses ISCAS’89 benchmark circuits for experiments and provides different property of experiment as run time, memory used of reachability analysis.

Combinational Circuit Equivalence Checking Using Binary Decision Diagram

This paper presents the background of Binary Decision Diagrams and its different type i.e. ROBDDs, ZBDDs, MTBDDs, SBDDs. It provides the introduction to CUDD (Colorado University Decision Diagram) which provides the functions to create BDD, ADD and ZDD. It also has functionality to manipulate between BDD, ADD and ZDD. And it is great tool to check equivalence between any combinational Boolean circuits. Finally this paper presents the results of circuit equivalence check between ISCAS’85 benchmark circuits.

Distributed Beamforming Feasibility Testing

Aim of this paper was to test the effectiveness of distributed beamforming over the beamforming and conventional way of transmission in different scenario. Our work presents a review of related work focused on implementing distributed beamforming using various techniques, also it measures and compares the amplitude as well as RSSI (Receiver Signal Strength Indicator) of the received signal for three different cases at different points in the particular area (known as grid) with respect to the reference node. The three different cases are; without beamforming (SISO), with beamforming (MISO), and with distributed beamforming (MISO).

This project is featured on WARP’s (Wireless open accesses research platforms) Project section. Please visit it Here.

Finite State Machine for Matrix Multiplier

Aim was to implement a circuit that will multiply a 3×4 matrix with its transpose. And deign two main block for this circuit Controller and Datapath. The circuit will compute B where B = AT * A. Each matrix element, aij is in 8-bit, 2’s complement form. Most of this design were done in Verilog and software used was Altera Quartus.

2.4 GHz CMOS Receiver

An attempt to design 2.4GHz CMOS receiver. CMOS receiver contains four major block, an LNA, Mixer, VCO and low pass filter. Designed 2.4GHz Single ended and Differential LNA with gain of 21.5dB and noise figure of 847.12mdB, 1.2GHz Local oscillators, and Mixer based on Gilbert cell double balanced topology.

Seven Segment Decoder for Four-Bit Input

The goal of this project is to design, synthesize, and layout a seven segment decoder that will handle the display of hexadecimal digits 0-F. This decoder will have four inputs (x3,x2,x1,x0) that represent the digits for a 4-bit binary number, and seven outputs (a-g) as shown in Figure below that activate the corresponding segments A-F on the display (also shown in Figure). Verilog code and test bench was designed to obtain optimal design. Then this design was synthesized using the Synopsys Design Compiler and layout was done using Cadence Encounter Place & Route.

Seven Segment Decoder Output Display
Seven Segment Decoder Output Display

8 bit Multiplier Transistor Level design and its Layout

Carry Save addition methodology is used for 8 bit multiplication. The main Aim was to design a multiplier which would work on low power. Our design worked on as low as 1.2V with power dissipation of 192.2μW and delay was 2.05ns. It was designed on 180nm CMOS technology, and Tested at multiplication rates up to 150MHz.

Micro-Controller Based Servo control Voltage Stabilizer

Developing Microcontroller (PIC16F877A) based volt meter and Ammeter to sense input and output voltage and current. Servo motor is used to control viper of auto transformer, TRIAC and its driver circuit are used to operate servo motor. Protection circuit was made of relay to cut of power in over load and under input voltage conditions. LCD Display to display various parameters and keyboard to externally set/change various set points. Developed complete schematic and PCB artwork of various circuits of project.

Temperature Controller

Temperature controller based on Microcontroller (P89V51RD2), Temperature sensing IC LM35, LCD to display temperature value, Bulb as heating element and Fan as cooling system. This project was done to understand, how to interface LCD, ADC and different IC with microcontroller and its programming.

Triple Power Supply

It has Regulated power supply consist of +/- 5V and +/- 12V, Variable Power Supply from 0V to 30V.As most of digital and analog IC runs on +/- 5V and +/-12V controlled power supply this basic project in first year of my Undergrad Came very Handy to operate and design circuits at home. This type of Power Supply Ready available in Market costs nearly around ₹1500/- to ₹2500/- while one can just make it for as low as ₹200/-.




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